1. Field of the Invention
The present invention relates to a method of manufacturing a flash memory device and specifically, to a method of manufacturing a flash memory device, which improves the reliability of the flash memory device by preventing source/drain selection transistors from being exposed while forming source/drain contacts.
2. Discussion of Related Art
In a NAND-type flash memory device, pluralities of transistors are arranged between drain contacts, those of which functions as drain selection transistors, and pluralities of transistors are arranged between source contacts, those of which functions as source selection transistors. And, pluralities of memory cells, e.g., 16, 32, or 64 memory cells are serially connected between the drain selection transistor and the source selection transistor, the construction of which forms a cell string. Here, while distances between memory cells of the cell string are same to each other, a distance between a memory cell and an adjacent drain or source selection transistor is designed to be wider than the distance between the memory cells on basis of the characteristics of the transistors.
FIGS. 1A through 1D are sectional diagrams illustrating sequential processing steps by a conventional method of manufacturing a flash memory device.
Referring to FIG. 1A, source/drain selection transistors 12 and a cell string 11 having plural memory cells are formed in a predetermined region over a semiconductor substrate 101. Here, a single memory cell is constructed of a tunnel oxide film 102, a floating gate 103, a dielectric film 104, and a control gate 105, those being stacked over the semiconductor substrate 101. Meantime, each of the source/drain selection transistors 12 is constructed of a gate oxide film 106 and a gate 107 that are stacked therein.
Referring to FIG. 1B, after depositing an oxide film 108 on the overall structure by means of a chemical vapor deposition (CVD) process, spacers are formed on sidewalls of the source/drain selection transistors 12 by conducting an etch-back process for the entire surface of the overall structure. The etching process for forming the spacers is carried out to completely disclose the semiconductor substrate 101 between the source/drain selection transistors 12. And then, a nitride film 109 is deposited on the overall structure, which is directed to prevent side damages on the source/drain selection transistors 12 during an etching process for forming source/drain contacts.
Referring to FIG. 1C, after forming an interlevel insulation film 110 on the overall structure, source/drain contacts 111 are formed by way of a lithography and etching process using a source/drain contact mask. However, if the etching process is conducted to completely disclose the semiconductor substrate 101 between the source/drain selection transistors 12, the nitride film 109 on the sidewalls of the source/drain selection transistors 12 is damaged to disclose the spacers, which causes the source/drain selection transistors 12 to be disclosed during the subsequent wet etching process.
Referring to FIG. 1D, a metal layer is deposited to fill up the source/drain contacts 111, forming plugs 112. Thus, the source/drain selection transistors 12 preliminarily disclosed are shorted to the plugs 112, which degrades the reliability of the flash memory device.